View HI3-0506A-5Z_8236379.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn3143.6 hi-506a, hi-507a, hi-508a, hi-509a 16-channel, 8-channel, differential 8-channel and differential 4-channel, cmos analog muxs with active overvoltage protection the hi-506a, hi-507a, hi-508a and hi-509a are analog multiplexers with active overvo ltage protection. analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. analog inputs can withstand constant 70v p-p levels with 15v supplies. digital inputs will also sustain continuous faults up to 4v greater than either supply. in addition, signal sources are protected from short circuiting should multiplexer su pply loss occur. each input presents 1k of resistance under this condition. these features make the hi-506a, hi-507a, hi-508a and hi-509a ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. all devices are fabricated with 44v dielectrically isolated cmos technology. the hi-506a is a single 16-channel multiplexer, the hi-507a is an 8-channel differential multiplexer, the hi-508a is a single 8-channel multiplexer and the hi-509a is a differential 4-channel multiplexer. if input overvoltage protection is not needed the hi-506/507/508/509 multiplexers are recommended. for further information see application note an520. features ? analog overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70v p-p ? no channel interaction during overvoltage ? maximum power supply . . . . . . . . . . . . . . . . . . . . . . 44v ? fail safe with power loss (no latch-up) ? break-before-make switching ? analog signal range . . . . . . . . . . . . . . . . . . . . . . . . 15v ? access time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns ? power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mw ? pb-free available (rohs compliant) applications ? data acquisition systems ? industrial controls ? telemetry data sheet october 30, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2004, 2007. all rights reserved
2 fn3143.6 october 30, 2007 ordering information part number part marking temp. range (c) package pkg. dwg. # hi1-0506a-2 hi1-506a-2 -55 to +125 28 ld cerdip f28.6 hi1-0506a-5 hi1-506a-5 0 to +75 28 ld cerdip f28.6 hi1-0506a-8 hi1-506a-8 -55 to +125 + 160 hour burn-in 28 ld cerdip f28.6 hi3-0506a-5 hi3-506a-5 0 to +75 28 ld pdip e28.6 HI3-0506A-5Z (note 1) hi3-506a-5z 0 to +75 28 ld pdip (note 2) (pb-free) e28.6 hi3-0507a-5 hi3-507a-5 0 to +75 28 ld pdip e28.6 hi3-0507a-5z (note 1) hi3-507a-5z 0 to +75 28 ld pdip (note 2) (pb-free) e28.6 hi1-0508a-8 hi1-508a-8 -55 to +125 + 160 hour burn-in 16 ld cerdip f16.3 hi3-0508a-5 hi3-508a-5 0 to +75 16 ld pdip e16.3 hi3-0508a-5z (note 1) hi3-508a-5z 0 to +75 16 ld pdip (note 2) (pb-free) e16.3 hi1-0509a-2 hi1-509a-2 -55 to +125 16 ld cerdip f16.3 hi1-0509a-5 hi1-509a-5 0 to +75 16 ld cerdip f16.3 hi1-0509a-8 hi1-509a-8 -55 to +125 + 160 hour burn-in 16 ld cerdip f16.3 hi3-0509a-5 hi3-509a-5 0 to +75 16 ld pdip e16.3 hi3-0509a-5z (note 1) hi3-509a-5z 0 to +75 16 ld pdip (note 2) (pb-free) e16.3 notes: 1. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering oper ations. intersil pb-free products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 2. pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. hi-506a, hi-507a , hi-508a, hi-509a
3 fn3143.6 october 30, 2007 pinouts hi-506a (cerdip, pdip) top view hi-507a (pdip) top view hi-508a (cerdip, pdip) top view hi-509a (cerdip, pdip) top view +v supply nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd v ref address a 3 out in 8 in 7 in 6 in 5 in 3 in 1 enable address a 0 address a 1 address a 2 -v supply in 4 in 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +v supply out b nc in 8b in 7b in 6b in 5b in 4b in 3b in 2b in 1b gnd v ref nc out a in 8a in 7a in 6a in 5a in 3a in 1a enable address a 0 address a 1 address a 2 -v supply in 4a in 2a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 enable -v supply in 1 in 2 in 3 out in 4 a 1 gnd +v supply in 5 in 6 in 7 in 8 a 2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 enable -v supply in 1a in 2a in 3a out a in 4a a 1 +v supply in 1b in 2b in 3b in 4b out b gnd hi-506a, hi-507a , hi-508a, hi-509a
4 fn3143.6 october 30, 2007 truth tables hi-506a a 3 a 2 a 1 a 0 en ?on? channel xxxxl none llllh 1 lllhh 2 llhlh 3 l lhhh 4 lhllh 5 lhlhh 6 lhhlh 7 lhhhh 8 hlllh 9 hllhh 10 hlhlh 11 hlhhh 12 hhl lh 13 hhlhh 14 hhhlh 15 hhhhh 16 hi-507a a 2 a 1 a 0 en ?on? channel pair xxxl none lllh 1 llhh 2 lhlh 3 lhhh 4 hllh 5 hlhh 6 hhlh 7 hhhh 8 hi-508a a 2 a 1 a 0 en ?on? channel xxxl none lllh 1 llhh 2 lhlh 3 lhhh 4 hllh 5 hlhh 6 hhlh 7 hhhh 8 hi-509a a 1 a 0 en ?on? channel pair x x l none llh 1 lhh 2 hlh 3 hhh 4 hi-506a, hi-507a , hi-508a, hi-509a
5 fn3143.6 october 30, 2007 functional diagrams hi-506a hi-507a hi-508a hi-509a decoder/ driver ? ? ? ? out in 1 in 2 in 16 protection a 0 a 1 a 2 a 3 ? en ? digital input level shift 5v ref v ref overvoltage clamp and signal isolation 1k 1k 1k decoder/ driver ? ? ? out in 1a in 8a in 1b protection a 0 a 1 a 2 ? en ? digital input level shift 5v ref v ref overvoltage clamp and signal isolation 1k 1k 1k in 8b 1k a out b decoder/ driver ? ? ? out in 1 in 2 in 8 protection a 0 a 1 a 2 ? en ? digital input level shift 5v ref overvoltage clamp and signal isolation 1k 1k 1k decoder/ driver ? ? out in 1a in 4a in 1b protection a 0 a 1 ? en ? digital input level shift 5v ref overvoltage clamp and signal isolation 1k 1k 1k in 4b 1k a out b hi-506a, hi-507a , hi-508a, hi-509a
6 fn3143.6 october 30, 2007 schematic diagrams address input buffer and level shifter address decoder level shifter p n p n n p n p v ref add in n p n p p n p n n p n p level shifted address to ttl reference circuit v+ r10 r9 q1 q4 d3 gnd overvoltage protection d2 r1 200 v- d1 v+ r2 r3 gnd v+ v- decode r4 r5 r7 r8 r6 p n a 0 or a 0 to n-channel device of the switch a 1 or a 1 a 2 or a 2 a 3 or a 3 enable pp pp p p v+ v- n n n n nn to p-channel device of the switch delete a 3 or a 3 input for hi-507a, hi-508a, hi-509a delete a 2 or a 2 input for hi-509a hi-506a, hi-507a , hi-508a, hi-509a
7 fn3143.6 october 30, 2007 multiplex switch schematic diagrams (continued) from decode n n v+ out in from decode overvoltage protection p d6 r11 1k v- d7 d4 d5 q6 n p q5 hi-506a, hi-507a , hi-508a, hi-509a
8 fn3143.6 october 30, 2007 absolute maximum rati ngs thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44v v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22v v- to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25v digital input voltage (v en , v a ) . . . . . . . . . . . . . (v-) -4v to (v+) +4v or 20ma, whichever occurs first analog signal (v in , v out ) . . . . . . . . . . . . . . (v-) -20v to (v+) +20v continuous current, in or out . . . . . . . . . . . . . . . . . . . . . . . . 20ma peak current, in or out, pulsed 1ms, 10% duty cycle (max) . . 40ma operating conditions temperature ranges hi-506a/507a/508a/509a-2, -8 . . . . . . . . . . . . . .-55c to +125c hi-506a/507a/508a/509a-5. . . . . . . . . . . . . . . . . . . 0c to +75c thermal resistance (typical, note 3) ja (c/w) jc (c/w) 28 ld cerdip package. . . . . . . . . . . . 55 18 16 ld cerdip package. . . . . . . . . . . . 75 22 28 ld pdip package . . . . . . . . . . . . . . 60 n/a 16 ld pdip package . . . . . . . . . . . . . . 90 n/a maximum junction temperature cerdip packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c pdip packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v ref pin = open; v ah (logic level high) = 4v; v al (logic level low) = 0.8v, unless otherwise specified. for test condi tions, consult test circuits section. parameter test conditions temp (c) -2, -8 -5 units min (note 12) typ max (note 12) min (note 12) typ max (note 12) dynamic characteristics access time, t a note 4 25 - 0.5 - - 0.5 - s full - - 1.0 - - 1.0 s break-before-make delay, t open note 4 25 25 80 - 25 80 - ns enable delay (on), t on(en) note 4 25 - 300 500 - 300 - ns full - - 1000 - - 1000 ns enable delay (off), t off(en) note 4 25 - 300 500 - 300 - ns full - - 1000 - - 1000 ns settling time, t s hi-506a and hi-507a to 0.1% 25 - 1.2 - - 1.2 - s to 0.01% 25 - 3.5 - - 3.5 - s hi-508a and hi-509a to 0.1% 25 - 1.2 - - 1.2 - s to 0.01% 25 - 3.5 - - 3.5 - s off isolation note 9 25 - 68 - - 68 - db channel input capacitance, c s(off) 25 -10- -10- pf channel output capacitance, c d(off) hi-506a 25 - 52 - - 52 - pf hi-507a 25 - 30 - - 30 - pf hi-508a 25 - 25 - - 25 - pf hi-509a 25 - 12 - - 12 - pf digital input capacitance, c a 25 -10- -10- pf input to output capacitance, c ds(off) 25 - 0.1 - - 0.1 - pf digital input characteristics input low threshold, ttl drive, v al note 4 full - - 0.8 - - 0.8 v input high threshold, v ah (note 11) note 4 full 4.0 - - 4.0 - - v hi-506a, hi-507a , hi-508a, hi-509a
9 fn3143.6 october 30, 2007 input leakage current (high or low), i a notes 4, 8 full - - 1.0 - - 1.0 a mos drive, v al , hi-506a/hi-507a v ref = +10v 25 - - 0.8 - - 0.8 v mos drive, v ah , hi-506a/hi-507a v ref = +10v 25 6.0 - - 6.0 - - v analog channel characteristics analog signal range, v in note 4 full -15 - +15 -15 - +15 v on resistance, r on notes 4, 5 25 - 1.2 1.5 - 1.5 1.8 k full - 1.5 1.8 - 1.8 2.0 k off input leakage current, i s(off) notes 4, 6 25 - 0.03 - - 0.03 - na full - - 50 - - 50 na off output leakage current, i d(off) notes 4, 6 25 - 0.1 - - 0.1 - na hi-506a full - - 300 - - 300 na hi-507a full - - 200 - - 200 na hi-508a full - - 200 - - 200 na hi-509a full - - 100 - - 100 na i d(off) with input overvoltage applied note 7 25 - 4.0 - - 4.0 - na full - - 2.0 - - - a on channel leakage current, i d(on) notes 4, 6 25 - 0.1 - - 0.1 - na hi-506a full - - 300 - - 300 na hi-507a full - - 200 - - 200 na hi-508a full - - 200 - - 200 na hi-509a full - - 100 - - 100 na differential off output leakage current, i diff , (hi-507a, hi-509a only) full - - 50 - - 50 na power supply characteristics current, i+ notes 4, 10 full - 0.5 2.0 - 0.5 2.0 ma current, i- notes 4, 10 full - 0.02 1.0 - 0.02 1.0 ma power dissipation, p d full - 7.5 - - 7.5 - mw notes: 4. 100% tested for dash 8. leakage currents not tested at -55c. 5. v out = 10v, i out = + 100 a. 6. 10na is the practical lower limi t for high speed measurement in the production test environment. 7. analog overvoltage = 33v. 8. digital input leakage is primarily due to the clamp diodes (see schematic). typi cal leakage is less than 1na at +25c. 9. v en = 0.8v, r l = 1k, c l = 15pf, v s = 7v rms , f = 100khz. 10. v en , v a = 0v or 4v. 11. to drive from dtl/ttl circuits, 1k pull-up resistors to +5v supply are recommended. 12. parts are 100% tested at +25c. over-temperature limits established by characterizati on and are not production tested. electrical specifications supplies = +15v, -15v; v ref pin = open; v ah (logic level high) = 4v; v al (logic level low) = 0.8v, unless otherwise specified. for test condi tions, consult test circuits section. (continued) parameter test conditions temp (c) -2, -8 -5 units min (note 12) typ max (note 12) min (note 12) typ max (note 12) hi-506a, hi-507a , hi-508a, hi-509a
10 fn3143.6 october 30, 2007 test circuits and waveforms t a = +25c, v supply = 15v, v ah = 4v, v al = 0.8v, v ref = open, unless otherwise specified figure 1a. test circuit figure 1b. on resistance vs analog input voltage figure 1c. normalized on resistance vs supply voltage figure 1. on resistance figure 2a. leakage current vs temperature figure 2b. i d(off) test circuit (note 13) 100 a out in v in r on = v 2 100 a v 2 -10 analog input (v) on resistance (k ) -8 246810 -6 -4 -2 0 1.4 1.3 1.2 1.1 1.0 0.9 0.8 +125c +25c -55c 0.7 0.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 normalized resistance (referred to value at 15v) 7 8 9 101112131415 supply voltage ( v) 56 -55c to +125c v in = +5v 100na 10na 1na 100pa 10pa leakage current 25 50 75 100 125 temperature ( c ) off output current i d(off) off input leakage current i s(off) on leakage current i d(on) i d(off) a 10v +0.8v en out 10v hi-506a, hi-507a , hi-508a, hi-509a
11 fn3143.6 october 30, 2007 figure 2c. i s(off) test circuit (note 13) figure 2d. i d(on) test circuit (note 13) note: 13. two measurements per channel: 10v and + 10v. (two measurements per device for i d(off) 10v and + 10v.) figure 2. leakage currents figure 3a. analog input overvoltage characteristics figure 3b. test circuit figure 3. analog input overvoltage characteristics figure 4a. on channel current vs vo ltage figure 4b. test circuit figure 4. on channel current test circuits and waveforms t a = +25c, v supply = 15v, v ah = 4v, v al = 0.8v, v ref = open, unless otherwise specified (continued) 10v 10v +0.8v en a out i s(off) out i d(on) a 10v 4v en a 0 a 1 10v 15 18 21 24 27 30 33 36 analog input overvoltage ( v) analog input current (ma) 18 15 12 9 0 6 3 output off leakage current (na) 5 4 3 2 1 0 analog input current (i in ) output off leakage current id (off) 6 7 a v in a i in i d(off) 024 68101214 0 14 12 10 8 6 4 2 voltage across switch ( v) switch current (ma) -55c +25c +125c a v in hi-506a, hi-507a , hi-508a, hi-509a
12 fn3143.6 october 30, 2007 figure 5a. supply current vs toggle frequency ? similar connection for hi-507a/hi-508a/hi-509a figure 5b. test circuit figure 5. dynamic supply current figure 6a. access time vs logic level (high) ? similar connection for hi-507a/hi-580a/hi-509a figure 6b. test circuit figure 6c. measurement points figure 6d. waveforms figure 6. access time test circuits and waveforms t a = +25c, v supply = 15v, v ah = 4v, v al = 0.8v, v ref = open, unless otherwise specified (continued) 8 6 4 2 0 1k toggle frequency (hz) supply current (ma) 10k 100k 1m 10m v supply = 10v v supply = 15v +15v/+10v v+ v- in 1 in 2 in 8/in 16 out a 0 en a 1 10 14 m pf a 3 a 2 50 v a +4v gnd a -15v/-10v a -i supply +i supply 10v/5v thru in 7/in 15 hi-506a ? 10v/ 5v 900 700 500 300 3 access time (ns) logic level (high) (v) 579 15 13 11 800 600 400 4 6 8 10 12 14 v ref = open for logic high level 6v v ref = logic high for logic high levels > 6v 10v +15v v+ v- in 1 in 2 thru in 16 out a 0 en a 1 10 50 k pf a 3 a 2 50 v a +4v gnd -15v 10v in 7/in 15 hi-506a ? v ref 1 / 2 v ah v ah = 4.0v 10% +10v 0v output -10v t a address drive (v a ) 200ns/div. v a input 2v/div. output 5v/div. s 1 on s 16 on hi-506a, hi-507a , hi-508a, hi-509a
13 fn3143.6 october 30, 2007 figure 7a. test circuit figure 7b. measurement points figure 7c. waveforms figure 7. break-before-make delay test circuits and waveforms t a = +25c, v supply = 15v, v ah = 4v, v al = 0.8v, v ref = open, unless otherwise specified (continued) in 1 in 2 thru in 8/in 16 out a 0 en a 1 50pf 1k v out a 3 a 2 50 v a +4.0v gnd in 7/in 15 hi-506a ? ? similar connection for hi-507a/hi-508a/hi-509a +5v 50% 50% v ah = 4.0v 0v output address drive (v a ) t open s 1 on s 16 on v a input 2v/div. output 0.5v/div. 100ns/div. hi-506a, hi-507a , hi-508a, hi-509a
14 fn3143.6 october 30, 2007 figure 8a. test circuit figure 8b. measurement points figure 8c. waveforms figure 8. enable delays test circuits and waveforms t a = +25c, v supply = 15v, v ah = 4v, v al = 0.8v, v ref = open, unless otherwise specified (continued) in 1 in 2 thru in 8 /in 16 out a 0 en a 1 50pf a 3 a 2 v a gnd 1k +10v in 7/in 15 hi-506a ? ? similar connection for hi-507a//hi-508a/hi-509a 50 v out v ah = 4.0v 0v output t off(en) t on(en) 10% 50% 50% 90% enable drive (v a ) 0v disabled output 2v/div. 100ns/div. enable drive 2v/div. enabled (s 1 on) hi-506a, hi-507a , hi-508a, hi-509a
15 fn3143.6 october 30, 2007 die characteristics die dimensions: 159 mils x 83.9 mils metallization: type: cual thickness: 16k ? 2k ? substrate potential (note): -v supply passivation: silox: 12k ? 2k ? nitride: 3.5k ? 1k ? worst case current density: 1.4 x 10 5 a/cm 2 transistor count: 485 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left floating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layouts hi-506a hi-507a in 9 in 10 in 11 in 12 in 13 in 14 in 15 in 16 v- (27) +v (1) nc (2) in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 en a 0 a 1 a 2 v ref gnd (18) (17) (16) (15) (13) (12) (19) (20) (21) (22) (23) (24) (25) (26) (4) (5) (6) (7) (8) (9) (10) (11) out (28) a 3 (14) in 1b in 2b in 3b in 4b in 5b in 6b in 7b in 8b v- (27) +v (1) out b(2) in 1a in 2a in 3a in 4a in 5a in 6a in 7a in 8a en a 0 a 1 a 2 nc v ref gnd (18) (17) (16) (15) (14) (13) (12) (19) (20) (21) (22) (23) (24) (25) (26) (4) (5) (6) (7) (8) (9) (10) (11) out a (28) hi-506a, hi-507a , hi-508a, hi-509a
16 fn3143.6 october 30, 2007 die characteristics die dimensions: 108 mils x 83 mils metallization: type: cual thickness: 16k ? 2k ? substrate potential (note): -v supply passivation: silox: 12k ? 2k ? nitride: 3.5k ? 1k ? worst case current density: 1.4 x 10 5 a/cm 2 transistor count: 253 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left floating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layouts hi-508a hi-509a in 6 in 7 in 8 out in 4 in 3 in 1 in 2 -v a 0 a 1 a 2 en in 5 gnd +v (11) (10) (9) (8) (7) (6) (12) (13) (14) (5) (4) (3) (15) (16) (1) (2) in 3b in 4b out b out a in 4a in 3a in 1a in 2a -v a 0 a 1 gnd en in 2b +v in 1b (11) (10) (9) (8) (7) (6) (12) (13) (14) (5) (4) (3) (15) (16) (1) (2) hi-506a, hi-507a , hi-508a, hi-509a
17 fn3143.6 october 30, 2007 hi-506a, hi-507a , hi-508a, hi-509a ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f28.6 mil-std-1835 gdip1-t28 (d-10, configuration a) 28 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a- 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 1.490 - 37.85 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 -7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2, 3 n28 288 rev. 0 4/94
18 fn3143.6 october 30, 2007 hi-506a, hi-507a , hi-508a, hi-509a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.250 - 6.35 4 a1 0.015 - 0.39 -4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 -5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00
19 fn3143.6 october 30, 2007 hi-506a, hi-507a , hi-508a, hi-509a ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f16.3 mil-std-1835 gdip1-t16 (d-2, configuration a) 16 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 0.840 - 21.34 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 -7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2, 3 n16 168 rev. 0 4/94
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3143.6 october 30, 2007 hi-506a, hi-507a , hi-508a, hi-509a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93

▲Up To Search▲

Price & Availability of HI3-0506A-5Z

	To Download HI3-0506A-5Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .